A ferroelectric non-volatile memory cell consists of a select, or access, transistor and a storage capacitor whose dielectric is made of a ferroelectric material film.
By applying an electric field of sufficient strength across the storage capacitor, the ferroelectric material is polarized in the direction of the electric field, and the acquired polarization is retained also after the electric field is removed. If an electric field of sufficient strength and direction opposite to the existing polarization is subsequently applied, the ferroelectric material becomes and remains polarized in such an opposite direction even after the electric field removal.
The effect of the polarization is a non-zero charge per unit storage capacitor area, which exists even when no voltage is applied across the capacitor and does not disappear in time. Information can thus be stored in the memory cell by associating the two opposite directions of polarization of the storage capacitor ferroelectric material with the two logic states “1” and “0”.
Due to the similarity of the ferroelectric non-volatile memory cell with the dynamic RAM (DRAM) memory cell, the former is also referred to as ferroelectric RAM or FeRAM.
Two families of FeRAMs are known in the art, which differ from each other for the number of memory cells employed to store a single data bit.
FeRAMs of a first family use a single memory cell as a bit storage unit, and are for this reason also referred to as “1T1C” (one transistor, one capacitor). Thanks to the simplicity of the bit storage unit, this kind of approach is suitable for achieving very large memory sizes, of the order of megabits.
The process of reading a “1T1C” FeRAM cell involves a sharing of the charge of the memory cell storage capacitor with the parasitic capacitance of the respective bit line of the memory cell array. A voltage thus develops on the bit line that, through the respective select transistor, is electrically connected to the storage capacitor. The bit line voltage can take one of two different values, depending on the polarization of the storage capacitor. A sense amplifier, typically a comparator fed with the bit line voltage and with a reference voltage, discriminates between the two possible voltage values and provides the stored data bit by comparing the bit line voltage to the reference voltage.
A problem with the “1T1C” approach is the difficulties inherent in the generation of the reference voltage to be supplied to the sense amplifier. The reference voltage must be sufficiently accurate for discriminating between the two voltage values, which can develop on the bit line. In particular, the difficulties arise from the fact that the reference voltage must assure the possibility of discriminating between the two voltage values in any condition of temperature, supply voltage, process variations and storage capacitor degradation within the specified ratings. In order to comply with these requirements, complex circuitry must be provided for, which has a negative impact on the memory chip size. Another problem affecting the “1T1C” approach is that the read margin, i.e. the difference between the two possible voltage values that develop on the bit line, decreases as the bit line length increases, due to the increase in the bit line parasitic capacitance.
A second family of FeRAMs has bit storage units made up of two memory cells, and is for this reason referred to as “2T2C” (two transistors, two capacitors) or “fully differential”. Considering a generic bit storage unit, the two storage capacitors are at any time polarized in mutually opposite directions (i.e., they store opposite logic states), except during the read and write operations. This allows having a reference quantity, which, during a read operation, can be used to discriminate between the two different logic states stored in the storage information unit.
This bit storage unit architecture does not suffer of the problems of the “1T1C” one, since no reference levels are needed for sensing the information stored in the bit storage unit. For this reason, this architecture is also referred to as “self-referenced”.
A read cycle of a fully differential storage unit provides for initially bringing to a reference voltage (the ground voltage of the memory device) the two bit lines containing the accessed storage unit. Then, a same electric field is applied to the two storage capacitors of the information storage unit, by raising the capacitor plates not connected to the bit lines to a sufficiently high voltage (typically the supply voltage VDD of the memory device chip). Depending on their polarization state, one of the two capacitors is always subjected to a polarization state reversal or switching. The potential of the bit line coupled to the switching capacitor is higher compared to that of the bit line coupled to the non-switching capacitor.
The sensing circuit typically comprises two inverters connected in a latch configuration, with inputs connected to the two bit lines. The latch, when activated, amplifies the differential voltage of the two bit lines, raising the bit line coupled to the switching capacitor to the latch supply voltage (normally, the memory device supply voltage VDD) and grounding the other bit line.
After the latch has been activated and the bit lines have been brought one to the latch supply voltage, the other to the ground, the plates of the storage capacitors not connected to the bit lines are brought to the ground voltage, so as to restore the initial polarization state in the switching capacitor.
It can be appreciated that during a read operation one of the storage capacitors, namely the one which undergoes a polarization state switch when the electric field is applied thereto, goes through the entire hysteresis loop of the ferroelectric material. This increases the fatigue of the information storage unit, causing a relatively fast degradation thereof.